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TECHNICAL NOTE
Audio Accessory ICs
Karaoke/Surround Digital Echo
BU9253AS/FS, BU9262AFS
Description The Karaoke/Surround Digital Echo IC incorporates a digital delay circuit, an input/output mixing circuit, supporting Karaoke echo and surround system, all in a single chip. BU9253AS/FS has functions required by Karaoke echo system, and BU9262AFS has various functions required for surround / echo system.
Features BU9253AS/FS 1) Digital delay time : 131ms (fCLK = 375kHz) 2) Built-in mixing circuit for adding original sound and echo sound 3) Echo mix ratio settable by DC voltage 4) Built-in amplifier circuit for structuring input/output secondary LPF 5) Microphone mute function (mute of mixing sound of original sound + echo sound) 6) Built-in CR oscillation circuit BU9262AFS 1) Digital delay time : 8-stage setting from 9.2ms to 192ms 2) Built-in input/output mixing circuit 3) Built-in feedback, delay volume circuit 4) Built-in input/output LPF 5) Serial interface 6) Auto mute circuit built in (action at power on, mode switching) 7) Built-in auto reset circuit at power on
Applications Radio cassette recorder, mini-component and karaoke systems.
Product lineup Parameter Supply voltage Oscillation frequency Current consumption Operating temperature range Package Digital delay Echo level BU9253AS 4.0V5.5V 375kHz 6mA -10+70 SDIP18 Fixed Fixed BU9253FS 4.0V5.5V 375kHz 6mA -10+70 SSOP-A16 Fixed Fixed BU9262AFS 4.5V5.5V 2MHz 20mA -10+70 SSOP-A32 Variable Variable
Ver.B Oct.2005
Absolute maximum ratings
BU9253AS Parameter Symbol Supply voltage VCCMAX Terminal voltage VIN Power dissipation PD Storage temperature TSTG * Reduce by 6.0 mW/C over 25C
Ratings 7.0 -0.3 VCC+0.3 600* -55 +125
Unit V V mW
BU9253FS Parameter Symbol Supply voltage VCCMAX Terminal voltage VIN Power dissipation PD Storage temperature TSTG * Reduce by 5.0 mW/C over 25C
Ratings 7.0 -0.3 VCC+0.3 500* -55 +125
Unit V V mW
BU9262AFS Parameter Supply voltage Terminal voltage Power dissipation Storage temperature
Symbol VCC VIN PD TSTG
Ratings 0.3 7.0 VSS - 0.3 VCC + 0.3 800* -55 +125
Unit V V mW
* Reduce by 8.0 mW/C over 25C Note: This IC is not designed to be radiation-resistant. Note: Operation is not guaranteed.
Operating conditions BU9253AS/FS Parameter Supply voltage Operating temperature Operating frequency
Symbol VCC Ta fC
Limits 4.0 5.5 -10 +70 375
Unit V kHz
BU9262AFS Parameter Operating supply range Operating temperature Operating frequency
Symbol VCC Ta fC
Limits 4.5 5.5 -10 +70 2
Unit V MHz
2/16
Electrical characteristics BU9253AS/FS Ta=25, VCC=5.0V, fC=375kHz, fin=1kHz, VI=-10dBV, ECHO VR pin=VCC, MUTE pin=VCC, unless otherwise specified.
Limits Parameter Symbol Min Circuit Current Voltage Gain 1 Voltage Gain 2 Output distortion 1 Output distortion 2 Output noise voltage 1 Output noise voltage 2 Maximum output voltage 1 Maximum output voltage 2 ICC GV1 GV2 THD1 THD2 VNO1 VNO2 VOM1 VOM2 VH MUTE control voltage VM VL Oscillation frequency fC -5.6 -1 1.4 1.4 3.8 1.6 0 Typ 6 -3.5 0 1.5 0.02 -80 -90 1.7 1.7 375 Max 12 -1.4 -1 3 0.1 -60 -80 5.0 2.8 0.7 mA dB dB % % dBV dBV Vrms Vrms V V V kHz No signal input Delay side total gain INOUT Through side total gain INOUTECHO VR pin=GND Delay side Through side ECHO VR pin=GND Delay side Rg=1k Through side Rg=1kECHO VR pin=GND Delay side THD=10% Through side THD=1%ECHO VR pin=GND H mode hold voltage MUTE pin DC M mode hold voltage MUTE pin DC L mode hold voltage MUTE pin DC Unit Condition
3/16
BU9262AFS (Ta = 25, VCC = 5V, VIN = 200mVrms, fin = 1kHz, fC = 2MHz, Rg = 600, unless otherwise specified.) Limits Typ. 20 0 0.6 1.0 1.2 1.5 -90 -87 -85 -83 1.0 3 0.17 -100 1.4 -90 -3 -90 0 0.01 -100 1.8 -90 35 25
Parameter Circuit current [Digital delay] Input/Output Gain
Symbol ICC
Min. -3 0.7 0 1.1 -6 -3 1.2 24 3.8 12 2.0 2.0 1.0 1.0 1.0
Max. 40 3 1.2 2.0 2.4 3.0 -75 -72 -70 -68 6 0.34 -90 -60 0 -60 3 0.03 -90 -65 1.2 50
Unit mA dB % % % % dBV dBV dBV dBV Vrms dB % dBV Vrms dB dB dB dB % dBV Vrms dB k V V k us us us us us
Condition No signal input
AV1 THD1 THD2 Output distortion THD3 THD4 VNO1 VNO2 Output noise voltage VNO3 VNO4 Maximum output voltage VMX1 [Delay volume "DSIG output"] Input//Output Gain AV5 Output distortion THD5 Output noise voltage VNO5 Maximum output voltage VMX5 Maximum attenuation ATT5 [Feedback volume] Input/Output Gain AV6 Maximum attenuation ATT6 [Line amplifier] Input/Output Gain AV7 Output distortion THD6 Output noise voltage VNO6 Maximum output voltage VMX6 Channel separation AVCS Input impedance ZI [Digital unit] Input"H"voltage VIH Input"L"voltage VIL Pull-up resistance Rd [Serial data] Clock width twCK Latch width twLT Data setup tdsu Data hold th Latch setup tlsu
tDL = 48ms30kHz LPF tDL = 96ms30kHz LPF tDL = 144ms30kHz LPF tDL = 192ms30kHz LPF tDL = 48msDINAUDIO tDL = 96msDINAUDIO tDL = 144msDINAUDIO tDL = 192msDINAUDIO THD = 10%30kHz LPF DLYVOL = MAX. 30kHz LPF DELAY OFFDINAUDIO THD = 10%30kHz LPF DLYVOL = MIN. DINAUDIO FBVOL = MAX. FBVOL = MIN. DINAUDIO
30kHz LPF DELAY OFFDINAUDIO THD = 10%30kHz LPF f = 400HzDINAUDIO
4/16
Reference data BU9253AS/FS
7.0 OUTPUT CURRENT : ICC [mA] 6.5 6.0 5.5 5.0 4.5 4.0 4.0 4.5 5.0 INPUT VOLTAGE : VCC [V] 5.5
Ta=25
385 380 375 370 365 360 355
Ta=25
2
Ta=25
Through side
OUTPUT GAIN : GV [dB] 0
OSC FREQUENCY : fC [kHz]
-2
-4
Delay side
-6
-8
4.0
4.5 5.0 INPUT VOLTAGE : VCC [V]
5.5
4.0
4.5 5.0 INPUT VOLTAGE : VCC [V]
5.5
Fig.1 Current consumption
VCC=5V / Ta=25
MIX OUT VOLTAGE : VOUT [dBv]
Fig.2 Oscillation frequency
VCC=5V / Ta=25
10 5 0 -5 -10 -15
Fig.3 Total gain characteristic
VCC=5V / Ta=25
4.5 MUTE THRESHOLD : MTH [V] 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
10 0
Mute
-20 -30 -40 -50 -60 -70 -80 -90 0.0 1.0 2.0 3.0 4.0 ECHO VR VOLTAGE : VR [V] 5.0
Mute & OSC stop
4.0 4.5 5.0 INPUT VOLTAGE : VCC [V] 5.5
OUTPUT GAIN : VOUT[dB]
-10
-20 0.1
1.0 INPUT FREQUENCY: FIN [kHz]
10.0
Fig.4 Mute pin threshold
VCC=5V / Ta=25
20 OUTPUT LEVEL : VOUT [dB]
Fig.5 ECHO VR characteristic
VCC=5V / Ta=25
Fig.6 A/D frequency characteristic
VCC=5V / Ta=25
20 OUTPUT LEVEL : VOUT [dB] 10 0 -10 -20 -30 -40
1K 10K 100K 1M 10M
5.5 OUTPUT LEVEL:VOUT[Vpp] 5.0 4.5 4.0 3.5 3.0 2.5
1K 10K 100K 1M 10M
10 0 -10 -20 -30 -40 INPUT FREQUENCY : FIN [Hz]
THD=%
1.0
INPUT FREQUENCY : FIN [Hz]
10.0 100.0 OUTPUT LOAD : RLOAD [k]
Fig.7 LPF operation amplifier frequency characteristic
VCC=5V / Ta=25
6 OUTPUT VOLTAGE : VOUT [V]
Fig.8 MIX operation amplifier frequency characteristic
VCC=5V / Ta=25
Fig.9 Through side output load drive characteristic
5.5 OUTPUT LEVEL : VOUT [Vpp] 5.0 4.5 4.0 3.5 3.0 2.5
VCC=5V / Ta=25
6 OUTPUT VOLTAGE : VOUT [V] 5 4 3 2 1 0
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 OUTPUT CURRENT : IOUT [mA]
5 4 3 2 1 0
THD=1%
-1.5
-1.0 -0.5 0.0 0.5 1.0 1.5 OUTPUT CURRENT : IOUT [mA]
1.0
10.0 100.0 OUTPUT LOAD : RLOAD [k]
Fig.10 LPF operation amplifier output performance
Fig.11 MIX operation amplifier output performance 5/16
Fig.12 Delay side output load drive characteristic
Reference data BU9262AFS
25 OUTPUT CURRENT : ICC [mA] Ta=25 VCC=5V / Ta=25 10 0 -10 -20 -30 -40 -50 4.5 4.7 4.9 5.1 5.3 5.5 10 INPUT VOLTAGE : VCC [V] 1K 100 INPUT FREQUENCY: FIN [Hz] 10K 10 0 -10 -20 -30 -40 -50 10 1K 10K 100K 100 INPUT FREQUENCY: FIN [Hz] VCC=5V / Ta=25
20
15
10
OUTPUT GAIN : VOUT[dB]
Fig.13 Circuit current
VCC=5V / Ta=25
Fig.14 PRE FILTER frequency characteristic
10 0 OUTPUT GAIN : AV7 [dB] -10 -20 -30 -40 -50
OUTPUT GAIN : VOUT[dB]
Fig.15 FBVOL frequency characteristic
0.1 OUTPUT DISTORTION : THD6 [%] VCC=5V / Ta=25
0 -10 LEVEL : DBO [dBV] -20 -30 -40 -50 -60 -70 -80
VCC=5V / Ta=25
Beginning at the top fIN=10kHz fIN=1f00Hz 0.01 fIN=100Hz
-80
-60
-40
-20
0
10
1K
100K
10M
0.001 -20
-15
-10
-5
0
AMPLITUDE : DBI [ dBV]
INPUT FREQUENCY: FIN [Hz]
INPUT LEVEL: LIN [dB]
Fig.16 Line amplifier linearity
VCC=5V / Ta=25
10 0 -10
Fig.17 Line amplifier frequency characteristic
10 0 -10 -20 -30 -40 -50 10 VCC=5V / Ta=25
OUTPUT DISTORTION : VOUT [%] 10
Fig.18 Line amplifier distortion characteristic
VCC=5V / Ta=25
OUTPUT GAIN : VOUT [dB]
LEVEL : DBO [dBV]
-20 -30 -40 -50 -60 -70 -80 -80 -60 -40 -20 0 AMPLITUDE : DBI [dBV]
1
Beginning at the top fIN=10kHz fIN=1f00Hz fIN=100Hz
0.1
1K
100K
10M
0.01 -20
-15
-10
-5
0
INPUT FREQUENCY: FIN [Hz]
INPUT LEVEL: RIN [dB]
Fig.19 MIX VOL linearity
VCC=5V / Ta=25 Cutoff=7kHz/Sampling=2MHz/6
Fig.20 MIX VOL frequency characteristic
100 VCC=5V / Ta=25 Cutoff=kHz/Sampling=2MHz/12 100
Fig.21 MIX VOL distortion characteristic
VCC=5V / Ta=25 Cutoff=kHz/Sampling=2MHz/24
100
OUTPUT THD : THD1 [%]
OUTPUT THD : THD2 [%]
OUTPUT THD : THD3 [%]
10
10
10
1
VIN=1kHz
1
VIN=1kHz
VIN=100Hz
1
VIN=1kHz VIN=100Hz
VIN=100Hz 0.1 -35 -30 -25 -20 -15 -10 -5 0 INPUT LEVEL: VIN [dB]
5
10
0.1 -35 -30 -25 -20 -15 -10 -5 0 5 INPUT LEVEL: VIN [dB]
10
0.1 -35 -30 -25 -20 -15 -10 -5 0 5 INPUT LEVEL: VIN [dB]
10
Fig.22 Input level vs distortion ratio characteristic 1
Fig.23 Input level vs distortion ratio characteristic 2 6/16
Fig.24 Input level vs distortion ratio characteristic 3
Pin description, Block diagram, Application circuit BU9253AS/FS Description of terminal
BU9253AS Pin No.
BU9253AS pin assignment
C R MT UE N C VC C A IN IN DT A IN O T DT U A L FO T DP U A L FIN DP M IN IX
18
17
16
15
14
13
12
11
10
BU9253FS
Pin No.
Symbol GND ECHO VR NC1 BIAS DAINT IN DAINT OUT DALPF IN DALPF OUT MIX OUT MIX IN ADLPF IN ADLPF OUT ADINT OUT ADINT IN VCC NC2 MUTE CR
Function GND pin Echo level DC control pin Not connected Analog unit DC bypath pin DA side integrator input pin DA side integrator output pin DA side LPF input pin DA side LPF output pin Mixing output of original sound and echo sound Original sound input pin of mixing amplifier AD side LPF input pin AD side LPF output pin AD side integrator output pin AD side integrator input pin VCC pin Not connected Mute control pin Oscillator CR pin
1 GND 2 ECHO VR 3 BIAS 4 DAINT IN 5 6 7 8 MIX OUT DAINT OUT DALPF IN DALPF OUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1
GD N
2
EH V CO R
3
N C
4
BS IA
5
D IN IN AT
6
D IN O T AT U
7
D L FIN AP
8
D L FO T AP U
9
M OT IX U
Fig.25 BU9253AS pin assignment
BU9253FS pin assignment
CR 16 MUTE 15 VCC 14 ADINT IN ADINT OUT ADLPF OUT 13 12 11 ADLPF IN 10 MIX IN 9
BU9253AS Block diagram, Application circuit
VCC VCC
Fig.26 BU9253FS pin assignment
R7 20k
+
100u C1 100p VCC
C5 0.012u
IN R3 22k 0.1u C3 0.01u R4 10k R5 20k
+
2.2u
+
R2 39k 18 C2 22u 17 16 15 14 13 12 C4 4700p 11
R6 8.2k
10
MUTE OSC
A/D
+
A/D side LPF operation amplifier A/DLPF
COUNTOR
SRAM
D/A side LPF operation amplifier D/ALPF
MIX
D/A
+ -
1
2 VCC VR1 10k
3
4
5 22u
6
7
C8 3300p
8
9 OUT
+
C6 0.01u
R8 2.2k
R9 10k 0.47u
R10 4.7k
+
2.2u
C7 0.01u
R11 15k
Fig.27 Application circuit 7/16
Pin description, Block diagram, Application circuit BU9262AFS Description of terminal
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol NC TESTB SCK SLT SI CLKO CLKI NC DSOUT TESTOUT LPF1I1 LPF1I2 LPF1O ADI ADO GND DAI DAO LPF2I1 LPF2I2 LPF2O VOIN DSIG VREF RCOUT LCOUT FBOUT RCIN LCIN VCC MICIN MIXIN Delay signal / volume input pin Delay signal output Analog reference voltage Rch output Lch output Feedback signal output Rch input Lch input Power source pin Microphone input (microphone amplifier output connected) Mix signal input LPF capacitor external pin ADC capacitor connection pin GND pin DAC capacitor connection pin LPF capacitor external pin Not connected Test negative logic input pin (normally "H" input) Serial clock input Serial latch input Serial data input Oscillation output pin Oscillation input pin Not connected Delay source output Test output pin (normally "L" output) Function
Block diagram
1 2 3 4 5 6
Clock DLYVOL
32 31
Test mode negative logic input Control
Serial control circuit
Input mixer selector
30 29 28 27
7 8 9 10 11 12 13 14
ADC LPF RAM
Output mixing

26 25 24 23
Reference voltage Reset
Test mode output
FBVOL
22 21
LPF
20 19
15 16
Processing
18
DAC
17
Fig.28 Block diagram Pin assignment
NC T EST B SCK S LT SI C LK O C LK I NC DSOUT T EST O U TESTOUT LP F1I1 LP F1I2 LP F1O AD I AD O GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 M IX IN M IC IN VC C LC IN R C IN FB O U T LC O U T RCOUT VR E F D S IG VO IN LP F2O LP F2I2 LP F2I1 D AO D AI
Fig.29 Pin assignment Application circuit
47u
0.1u 1 2 SERIAL CLOCK SERIAL LATCH SERIAL DATA R 2MHz R 7 8 9 1u NP 10 11 12 2200p 13 14 ADC 0.01u 15 16
Processing
DLYVOL
Test mode negative logic input
32 31 1u MIC IN
3 4 5 6 Clock
Serial control circuit
Input mixer selector
30 29 28 27 1u Rch IN 1u 0.33u R 1M Lch OUT 2.2u Rch OUT 2.2u Lch IN
Output mixing

Reference voltage
26 25 24 23 22 21

Test output FBVOL LPF RAM LPF
2.2u 47u 0.1u 2200p
DSIG
20 19
0.01u
18 DAC 17 0.01u 0.01u
Fig.30 Application circuit 8/16
Description of operations BU9253AS/FS OSC(Oscillator) Clock is generated by connecting external RC circuit. Clock is used for the delay counter. Mute control circuit (MUTE) By input voltage of the mute terminal, 3 statuses, that is, mute, mute release (operating), and clock stop & mute can be selected. COUNTER This counter is for generating delay time. It can generate delay time about 131ms at oscillation frequency Fclk = 375kHz. SRAM SRAM with 8Kbit capacity for generating the delay. A/D side LPF operation amplifier LPF can be structured by external RC, and band limit of signal to be input to A/D is available. A/D This digitalizes output signal of AD side LPF, and outputs it to SRAM. D/A side LPF operation amplifier LPF can be structured by external RC, and band limit of signal to be output to D/A is available. D/A This converts delayed audio digital data input from SRAM into analog signal. Mixing amplifier (MIX) This circuit is used for mixing delayed signals and (original sound) signals input from MIX IN. BU9262AFS Serial control circuit This serial I/F circuit is for setting each register. It can be controlled by serial 16bit data. It reads in SI at the rise of SCK, and latches data at the rise of SLT. No. D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 Delay time Mode Remarks Delay time setting "Refer to the separate table." ( D3D4 ) = ( LL )LR ( LL )LR ( LH )MIC ( HH )CLK OFF ( D5D6 ) = ( LL )FWD (L, R in phase) ( LL )REV (R in opposite phase) ( LH )MIC MIX ( HH )NORMAL H : output ON L : output OFF Delay signal / volume setting "Refer to the separate table." Feedback / volume setting "Refer to the separate table." (D5, D6) = (L, H) : latch Others are not latch 9/16
INPUT select "ISEL"
OUTPUT select "OSEL" Delay out "DOSW" Delay volume "DLYVOL" Feedback volume "FBVOL" Latch control
Delay time control circuit This circuit controls delay time. -8 delay time can be selected by register. D0 L H L H L H L H D1 L L H H L L H H D2 L L L L H H H H Delay time (Sampling frequency) 9.2msec (2MHz / 6) 15.4msec (2MHz / 6) 21.1msec (2MHz / 6) 30.0msec (2MHz / 6) 48.0msec (2MHz / 6) 96.0msec (2MHz / 12) 144.0msec (2MHz / 18) 192.0msec (2MHz / 24) LPF cutoff frequency
7kHz
3kHz
Delay signal volume circuit This is the delay signal volume circuit. 8 volume setting can be selected by register. D8 L H L H L H L H D9 L L H H L L H H D10 L L L L H H H H DLYVOL +3dB 0dB -3dB -6dB -9dB -12dB -15dB -dB
Feedback volume circuit This is the feedback volume circuit. 8 feedback volume setting can be selected by register. D11 L H L H L H L H D12 L L H H L L H H D13 L L L L H H H H FBVOL -3dB -5dB -7dB -9dB -11dB -13dB -15dB -dB
Input mixerselector circuit This mixes MIC IN, LCIN, RCIN, VOIN signals, and selects the output path by selector.
OSEL #2
LCIN
LCOUT
OSEL #3
RCIN
RCOUT
MRCIN
ISEL ADC Delay DAC
VOIN
FBVOL
OSEL #1
DLY VOL
DOSW
DSIG
Fig.31 Input mixer selector circuit 10/16
Output/ input LPF circuit
This is the LPF circuit connected to the ADC input unit and the DAC output unit. Delay time setting can be select by internal resistor. Delay amount 48.0msec or below 96.0msec or below Switch S1 S2 Resistance value 4.8k* 11.3k*
*Internal resistance precision is 30%. Pins 11, 19 1119 Pins 12, 20 1220 Pins 13, 21 1321
R1 R2 S1 R1 R2 S2 ()11 Note: In Pin 11, is an external capacity connection R1 R2
Fig.32 Input LPF / Output LPF circuit Auto mute circuit Delay output is muted during power on and delay time switching.
Timing chart BU9262AFS
Serial interface specification
SI
D0
D1
D12 D13 D14 D15
SCK
SLT
Fig.33 Serial interface specification Serial timing
SCK
twCK tdsu
twCK th tdsu
SI
SLT
twLT
Fig.34 Serial timing
11/16
Description of external components < BU9253AS/FS > (Refer to Fig. 27.) Echo level Echo signal level is determined by the gains of A/D side operation amplifier and the D/A operation amplifier, since there is no gain in A/D SRAM D/A. Path in applied circuit example, Gain at A/D side : R4 / R5 = 10K / 20K = 0.5 Gain at D/A side : R11 / R9 = 15K / 10K = 1.5 When the original signal is defined as 1, the echo signal level becomes the feedback ratio. Echo signal feed back ration = 0.5 x 1.5 = 0.75 = 75%
Echo level setting method
Echo level can be set by adjusting DC voltage by VR1. It does not change in low voltage range, therefore, R8 is added, and it can be adjusted by VR pot.
Clock frequency and delay time
Clock frequency and delay time are as the following equations. Sample frequency = clock frequency / 6 Delay time = (1 / sample frequency) x 8192 (SRAM 8192 bits) As an example, when clock frequency is 375kHz, then sample frequency is 375kHz / 6 = 62.5kHz. Therefore, the delay time is: Delay time = (1 / 62500) x 8192 = 131ms Clock frequency is determined by R2, C1 connected to CR terminal (pin 18 in BU9253AS, pin 16 in BU9253FS). When C, R are changed, oscillation frequency changes, but the delay time is kept fixed.
LPF frequency characteristic
When the band width is set too narrow, echo voice becomes worse, and when band width is set wide, A/D cannot be converted, and S/N becomes worse. Band width of applied circuit example is 2kHz.
A/D, D/A external capacitors C3, C6
Feedback is set by resistance and capacitor so that output follows even when input signal level and frequency of A/D, D/A change. Variation in the externally attached capacitor can influence the sound quality. A small capacitor can generate noise, while a capacitor that is too large will attenuate. In applied circuit example, 0.01uF is selected to avoid influence upon LPF.
Mute
Can be controlled by input voltage of MUTE pin. It takes more than one SRAM cycle for switching between mute mute release (L M H). It is necessary for initializing SRAM and insuring stable status before changing operating modes. MIX OUT output is muted, so original sound and echo sound output is stopped. MUTE pin H M L Mode Mute release (operating) Mute Clock stop & mute
In the applied circuit example, MUTE is set by R3, C2. In the specifications, voltage range of M is 1.6V ~ 2.8V, therefore, it is necessary to change R3,C2, and set the time of 1.6V ~ 2.8V over 131ms. In consideration of fluctuation, C2 = 22uF, R3 = 22k. When MUTE pin is controlled by the microcontroller, select M range to 1.6V ~ 2.8V and keep M level over 131ms.
Maximum signal input
When original signal and echo are in phase and mixed, both the signals are added to reach maximum output. In order not to clip this signal, the maximum output at power source voltage of 5V is about 4Vpp. When echo feedback ratio is 0.75, then maximum signal input becomes about 1.0Vpp. Vout MAX1(1A)xVin 1(10.75)xVin4Vpp Vin1Vpp
12/16
LPF and echo system gain
When the ratio of original signal and echo is changed, R5, R6, R9, R11 are also changed, and the characteristics of LPF change too. Therefore, it is necessary to change all the constants of LPF. In the case, to precisely measure the ratio of original signal and echo, remove R7, input signal around 500Hz without the influence of LPF from MIX IN, and compare it with the output of DALPF OUT.
R4 R11 C4 C8 R5 R9 IN C5 C7 R6 R10 OUT
fc =
1 2 C 4 C 5 R 4R 5 1 R 4R 5 + R4 R5 R 4R 5 R6 A2 = R11 R9 C 5R 4R 5 C4
Q=
QQ 0.7 generally about 0.7
A1 =
Echo signal amplitude ratio Fig.35 LPF and echo system gain
= A1 x A 2 = R 4 x R11 R5 x R9
Clock oscillation
As for C,R, tolerance should be below 5%. Note: If measurement is made by attachment a probe oscilloscope it might load the oscillator and reduce the oscillation frequency. * The set values in this document are for reference only. In the actual set, characteristics may change according to board layout, wiring, types of parts used, and therefore, in actual use, carry out sufficient verification with the actual devices.
13/16
Cautions on Use 1) Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. Operating conditions Characteristics are guaranteed under the conditions of each specified parameter. Reverse polarity connection of the power supply Connecting the of power supply in reverse polarity can damage IC. Take precautions when connecting the power supply lines. An external direction diode can be added. Power supply line Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line, separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the circuit, note that capacitance characteristic values are reduced at low temperatures. GND voltage Ground-GND potential should maintain at the minimum ground voltage level. Furthermore, no terminals (except SWOUT) should be lower than the GND potential voltage including an electric transients. Short circuit between terminals and GND or other devices Pay attention to the assembly direction of the ICs. Wrong mounting direction or shorts between terminals, GND, or other components on the circuits, can damage the IC. Operation in a strong electromagnetic field Using the ICs in a strong electromagnetic field can cause operation malfunction. Inspection with set PCB During testing, turn on or off the power before mounting or dismounting the board from the test Jig. Do not power up the board without waiting for the output capacitors to discharge. The capacitors in the low output impedance terminal can stress the device. Pay attention to the electro static voltages during IC handling, transportation, and storage. Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and breakdown of the input terminal. Therefore, pay thorough attention not to apply a voltage lower than the GND to the input terminals. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply a voltage lower than the power supply voltage to the input terminals, or a voltage within the guaranteed value of electrical characteristics.
2)
3)
4)
5)
6)
7)
8)
9)
10) Ground wiring pattern The power supply and ground lines must be as short and thick as possible to reduce line impedance. Fluctuating voltage on the power ground line may damage the device. 11) External capacitor When using external ceramic capacitors, consider degradation in the nominal capacitance value due to DC bias and changes in the capacitance with temperature.
14/16
Product designation
B
U
9
2
5
3
A
S
-
E
2
Part Number BU9253
Package type AS: SDIP18 FS: SSOP-A16 9 2 6 2 A F S -
Package and forming specifications E2: Embossed tape and reel
B
U
E
2
Part Number BU9262A
Package type FS: SSOP-A32
Package and forming specifications E2: Embossed tape and reel
SDIP18

Container
19.4 0.3 18 10
Tube 1000pcs Direction of products is fixed in a container tube.
Quantity
6.5 0.3
Direction of feed
7.62
3.95 0.3
0.51Min.
1
9
3.4 0.2
0.3 0.1
1.778 0.5 0.1 0 15
(Unit:mm)
Orders are available in complete units only.
SSOP-A16

Tape Quantity
6.60.2
6.20.3 1.50.1 4.40.2 0.11 0.3Min.
16 9
Embossed carrier tape 2500pcs E2
(Correct direction: 1pin of product should be at the upper left when you hold reel on the left hand, and you pull out the tape on the right hand)
Direction of feed
1
8
0.150.1 0.1
0.8
1234
1234
1234
1234
1234
1234
1234
1234
0.360.1
Reel
1pin
Direction of feed
Unit:mm)
Orders are available in complete units only.
SSOP-A32

Tape Quantity
13.6 0.2
32 17
Embossed carrier tape 2000pcs E2
(Correct direction: 1pin of product should be at the upper left when you hold reel on the left hand, and you pull out the tape on the right hand)
1.8 0.1 7.8 0.3 5.4 0.2 0.11
Direction of feed
0.3Min.
1
16
0.15 0.1 0.1
1234
1234
1234
1234
1234
1234
1234
1234
0.8
0.36 0.1
Reel
1pin
Direction of feed
Unit:mm)
Orders are available in complete units only.
15/16
16/16
Catalog No.05T411Be '06.4 ROHM C
Appendix
Notes
No technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of ROHM CO.,LTD. The contents described herein are subject to change without notice. The specifications for the product described in this document are for reference only. Upon actual use, therefore, please request that specifications to be separately delivered. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. Products listed in this document are no antiradiation design.
The products listed in this document are designed to be used with ordinary electronic equipment or devices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). Should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the NOTES specified in this catalog.
Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office.
ROHM Customer Support System
www.rohm.com
Copyright (c) 2008 ROHM CO.,LTD.
THE AMERICAS / EUROPE / ASIA / JAPAN
Contact us : webmaster@ rohm.co. jp
21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan
TEL : +81-75-311-2121 FAX : +81-75-315-0172
Appendix1-Rev2.0

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